1. Field of the Invention
The present invention generally relates to a stacked capacitor and method of making in high density DRAM circuit, and more particularly, to a method for making a high capacitance stacked capacitor in high density DRAM circuit.
2. Description of the Prior Art
A memory has two operations: electrical program and electrical erasure. In generally, the basic configuration of memory is composed of two major portions: the memory cell array and the peripheral circuit. The memory cell array for data storage is constructed by a plurality of memory cells regularly arranged in an array based on the intersected word lines and bit lines. The peripheral circuit provides the flash memory with functions such as power supply and data processing during operation. So how to improve the capacitance of DRAM (Dynamic Random Access Memory) becomes the most important objective of DRAM industry.
In the prior art, all uses polysilicon to form electrode of a stacked capacitor, and with the result that it can only use low dielectric constant materials for dielectric layer, such as NO, ONO, or the like. Then to use metal-insulator-metal (MIM) to improve the capacitance of stacked capacitor, for example, the U.S. Pat. No. 6,277,702 discloses a method of fabricating capacitor of a semiconductor device. Please refer to FIG. 1A to FIG. 1C, in which the method for fabrication is schematically illustrated. As shown in FIG. 1A, to begin with, there is provided a semiconductor substrate 1, on which a field oxide layer 2 is formed to define an active area and then an insulator layer 3 is deposited on it. By using a standard photolithography process to form a contact plug in the insulator layer 3. Depositing a conductor layer 5, a first barrier metal layer 6, and a first transition metal layer 7 in sequence and then using a standard photolithography process to form in which FIG. 1 shows. The conductor layer 5 is formed of polysilicon to a thickness of about 1000 to 6000 xc3x85. As shown in FIG. 1B, a second barrier metal layer is deposited on the insulator layer 3, the conductor layer 5, the first barrier metal layer 6, and the second transition metal layer 7. An etching back process is performed to form barrier metal spacer 8. The second barrier metal layer is made of the same material as the first barrier layer 6. A second transition metal is deposited on the resulting structure. The second transition metal is then etched back to form transition metal spacer 9. As shown in FIG. 1C, finally, depositing a high dielectric constant layer 10 on the resulting structure.
This invention further discloses a Metal-Insulator-Metal capacitor having higher capacitance and method of making.
It is the primary object of the present invention to provide a metal-insulator-metal (I) structure and fabrication so that to fabricate the high density DRAM.
In order to achieve the foregoing object, the present invention provides a method of making stacked capacitor in high density DRAM circuit, comprising the steps of:
forming a contact plug in an insulating layer on a semiconductor substrate;
forming a first conductor layer, a first barrier metal layer, a first transition metal layer, and a sacrificial layer in sequence;
patterning said first conductor layer, said first barrier metal layer, said first transition metal layer, and said sacrificial layer stopping on said insulating layer;
forming a second barrier metal layer and then etch back to form a barrier metal spacer;
removing said sacrificial layer to form a recess between said barrier metal spacer;
forming a second transition metal layer and then etch back to form a transition metal spacer; and
forming a high dielectric constant layer.
The present invention provides a method of making stacked capacitor in high density DRAM circuit, further comprising the step of:
depositing a silicon nitride layer as a chemical mechanical polishing (CMP) stopper.